1-- Literatur: Vorlesungsunterlagen EDS3 von Markus Pfaff (FH-Hagenberg)
2
3-- fuer synthetisierbare Entities sind signed, unsigned dem integer Datentyp
4-- vorzuziehen, denn diese werden aus den mehrwertigen std_logic gebildet
5-- ('U', '0', '1', ...)
6
7type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; -- vorzeichenlos
8type SIGNED is array (NATURAL range <>) of STD_LOGIC; -- vorzeichenbehaftet
9
10-- Arithmetik Operationen
11-- "+", "-", "*", "/", "mod", "rem", "abs"
12
13-- Vergleichsoperationen
14-- "<", ">", "<=", ">=", "=", "/="
15-- std_match
16
17-- Logik Operationen
18-- "and", "nand", "or", "nor", "xor", "xnor", "not"
19
20-- Schiebe/Rotier Operationen
21-- "sll", "sla", "srl", "sra", "rol", "ror"
22
23-- Resize Operatoinen
24 numeric_std std_logic_arith
25unsigned resize(arg,size) conv_unsigned(arg,size)
26signed resize(arg,size) conv_signed(arg,size)
27
28-- Konvertierungs Operationen
29-- unsigned -> natural
30 function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
31-- signed -> integer
32 function TO_INTEGER (ARG: SIGNED) return INTEGER;
33-- natural -> unsigned
34 function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
35-- integer -> signed
36 function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
37
38-- Typen Konvertieren
39std_logic_vector -> unsigned unsigned(arg) numeric_std
40 unsigned(arg) std_logic_arith
41
42std_logic_vector -> signed signed(arg)
43 signed(arg)
44
45unsigned -> std_logic_vector std_logic_vector(arg)
46 std_logic_vector(arg)
47
48signed -> std_logic_vector std_logic_vector(arg)
49 std_logic_vector(arg)
50
51integer -> unsigned to_unsigned(arg,size)
52 conv_unsigned(arg,size)
53
54integer -> signed to_signed(arg,size)
55 conv_signed(arg,size)
56
57unsigned -> integer to_integer(arg)
58 conv_integer(arg)
59
60signed -> integer to_integer(arg)
61 conv_integer(arg)
62
63integer -> std_logic_vector integer
64 -> unsigned/signed
65 -> std_logic_vector
66
67std_logic_vector -> integer std_logic_vector
68 -> unsigned/signed
69 ->integer
70
71unsigned + unsigned -> std_logic_vector std_logic_vector(arg1 + arg2)
72 arg1 + arg2
73
74signed + signed -> std_logic_vector std_logic_vector(arg1 + arg2)
75 arg1 + arg2
76
77-- Literale fuer signed/unsigned
78to_unsigned(93, 8)
79"0011001100110011" -- bei signed mit Vorzeichen
80b"0011001100110011" -- Binaer
81x"F8C43E0" -- Hexadecimal
82
83
84-- synchron sequentielle Logik
85 ABCffs: process (Clk, nResAsync) is -- erzeugt pro gespeicherten
86 begin -- Signal ein flankenge-
87 if nResAsync = cnActivated then -- steuertes D-FF
88 A <= '0';
89 B <= '0';
90 C <= '0';
91 elsif Clk'event and Clk='1' then
92 A <= NextA;
93 B <= NextB;
94 C <= NextC;
95 end if;
96 end process ABCffs;
97
98 CalcNext: process (A, B, C) is -- rein kombinatorisch,
99 begin -- also kein Speicher und
100 NextA <= A and B; -- keine Latches!
101 NextB <= B and C;
102 NextC <= C and A;
103 end process CalcNext;
104
105
106 constant DefaultState : std_ulogic_vector(2 downto 0) := "000";
107
108 StateReg: process (Clk, nResAsync) is
109 begin
110 if nResAsync = cnActivated then
111 State <= DefaultState;
112 elsif Clk'event and Clk='1' then
113 State <= NextState;
114 end if;
115 end process StateReg
116
117 NextStateLogic: process (State) is
118 begin
119 case State is
120 when "000" => NextState <= "100";
121 when "100" => NextState <= "010";
122 when "010" => NextState <= "001";
123 when "001" => NextState <= "011";
124 when "011" => NextState <= "111";
125 when "111" => NextState <= "000";
126 when others => NextState <= "XXX";
127 end process CalcNextState;
128
129
130-- synchron sequentielle Logik (1 Prozess)
131 library ieee;
132 use ieee.std_logic_1164.all;
133 use ieee.numeric_std.all;
134 use work.global.all;
135
136 entity Counter is
137 port (iResetAsync : in std_ulogic;
138 iClk : in std_ulogic;
139 oCount : out Unsigned(3 downto 0));
140 end entity Counter;
141
142 architecture Rtl of Counter is
143 signal Count : unsigned(3 downto 0);
144 begin
145 CountUp: process (iResetAsync, iClk) is
146 begin
147 if iResetAsync = cActivated then
148 Count <= (others => '0');
149 elsif iClk'event and iClk='1' then
150 if Count=x"9" then
151 Count <= (others => '0');
152 else
153 Count <= Count + 1;
154 end if;
155 end if;
156 end process CountUp;
157
158 oCount <= Count;
159 end architecture Rtl;
160
161
162-- synchron sequentielle Logik (mit Eingaengen)
163 architecture Rtl of Counter is
164 signal Count : unsigned(3 downto 0);
165 begin
166 oCount <= Count;
167 Counting: process (iResetAsync, iClk) is
168 begin
169 if iResetAsync = c then
170 Count <= to_unsigned(0, Count'length);
171 elsif iClk'event and iClk='1' then
172 if iZero = cActivated then
173 Count <= to_unsigned(0, Count'length);
174 elsif iCountUp = cActivated then
175 if Count = x"9" then
176 Count <= to_unsigned(0, Count'length);
177 else
178 Count <= Count + 1;
179 end if;
180 else
181 if Count = x"0" then
182 Count <= x"9";
183 else
184 Count <= Count - 1;
185 end if;
186 end if;
187 end if;
188 end process Counting;
189 end architecture Rtl;
190
191
192-- Moore FSM
193 package Global is
194 constant cActivated : std_ulogic := '1';
195 constant cInctivated : std_ulogic := '0';
196 type aState is (Standing, WalkingForward,
197 WalkingBackwards, Thinking);
198 end package Global;
199
200 library IEEE;
201 use IEEE.std_logic_1164.all;
202 use work.global.all;
203 entity WalkAndThinkMachine is
204 port(iResetAsync : in std_ulogic;
205 iClk : in std_ulogic;
206 iForth,
207 iBack : in std_ulogic;
208 oBusy : out std_ulogic;
209 oState : out aState);
210 end entity WalkAndThinkMachine;
211 architecture Rtl of WalkAndThinkMachine is
212 signal State, NextState : aState;
213 begin
214 oState <= State;
215
216 NextStateAndOutput: process (State, iForth, iBack) is
217 begin
218 -- default settings
219 NextState <= State;
220 oBusy <= cInactivated;
221
222 case State is
223 when Standing =>
224 if iForth = cActivated then
225 NextState <= WalkingForward;
226 elsif iBack = cActivated then
227 NextState <= WalkingBackwards;
228 end if;
229 when WalkingForward =>
230 if iForth = cActivated then
231 NextState <= WalkingForward;
232 elsif iBack = cActivated then
233 NextState <= WalkingBackwards;
234 end if;
235 when WalkingBackwards =>
236 if iForth = cActivated then
237 NextState <= Thinking;
238 elsif iBack = cActivated then
239 NextState <= WalkingBackwards;
240 end if;
241 when Thinking =>
242 oBusy <= cActivated;
243 if iForth = cActivated then
244 NextState <= Standing;
245 end if;
246 end case;
247 end process NextStateAndOutput;
248
249 StateReg: process (iResetAsync, iClk) is
250 begin
251 if iResetAsync = cActivated then
252 State <= Standing;
253 elsif iClk'event and iClk='1' then
254 State <= NextState;
255 end if;
256 end process StateReg;
257 end architecture Rtl;
258
259
260-- Mealy FSM
261 package Global is
262 constant cActivated : std_ulogic := '1';
263 constant cInctivated : std_ulogic := '0';
264 type aState is (WalkingForward, WalkingBackwards, Drinking);
265 end package Global;
266
267 library IEEE;
268 use IEEE.std_logic_1164.all;
269 use work.global.all;
270
271 entity WalkAndDrinkMachine is
272 port(iResetAsync : in std_ulogic;
273 iClk : in std_ulogic;
274 iForth,
275 iBack : in std_ulogic;
276 oGulp : out std_ulogic;
277 oState : out aState);
278 end entity WalkAndDrinkMachine;
279
280 architecture Rtl of WalkAndDrinkMachine is
281 signal State, NextState : aState;
282 begin
283 oState <= State;
284
285 NextStateAndOutput: process (State, iForth, iBack) is
286 begin
287 -- default settings
288 NextState <= State;
289 oGulp <= cInactivated;
290
291 case State is
292 when Drinking =>
293 oGulp <= cActivated;
294 if iForth = cActivated then
295 NextState <= WalkingForward;
296 elsif iBack = cActivated then
297 NextState <= WalkingBackwards;
298 end if;
299 when WalkingForward =>
300 if iForth = cActivated then
301 NextState <= WalkingForward;
302 elsif iBack = cActivated then
303 NextState <= Drinking;
304 oGulp <= cActivated;
305 end if;
306 when WalkingBackwards =>
307 if iForth = cActivated then
308 NextState <= Drinking;
309 oGulp <= cActivated;
310 end if;
311 end case;
312 end process NextStateAndOutput;
313
314 StateReg: process (iResetAsync, iClk) is
315 begin
316 if iResetAsync = cActivated then
317 State <= Drinking;
318 elsif iClk'event and iClk='1' then
319 State <= NextState;
320 end if;
321 end process StateReg;
322 end architecture Rtl;
