-- Literatur: Vorlesungsunterlagen EDS3 von Markus Pfaff (FH-Hagenberg) -- fuer synthetisierbare Entities sind signed, unsigned dem integer Datentyp -- vorzuziehen, denn diese werden aus den mehrwertigen std_logic gebildet -- ('U', '0', '1', ...) type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; -- vorzeichenlos type SIGNED is array (NATURAL range <>) of STD_LOGIC; -- vorzeichenbehaftet -- Arithmetik Operationen -- "+", "-", "*", "/", "mod", "rem", "abs" -- Vergleichsoperationen -- "<", ">", "<=", ">=", "=", "/=" -- std_match -- Logik Operationen -- "and", "nand", "or", "nor", "xor", "xnor", "not" -- Schiebe/Rotier Operationen -- "sll", "sla", "srl", "sra", "rol", "ror" -- Resize Operatoinen numeric_std std_logic_arith unsigned resize(arg,size) conv_unsigned(arg,size) signed resize(arg,size) conv_signed(arg,size) -- Konvertierungs Operationen -- unsigned -> natural function TO_INTEGER (ARG: UNSIGNED) return NATURAL; -- signed -> integer function TO_INTEGER (ARG: SIGNED) return INTEGER; -- natural -> unsigned function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED; -- integer -> signed function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED; -- Typen Konvertieren std_logic_vector -> unsigned unsigned(arg) numeric_std unsigned(arg) std_logic_arith std_logic_vector -> signed signed(arg) signed(arg) unsigned -> std_logic_vector std_logic_vector(arg) std_logic_vector(arg) signed -> std_logic_vector std_logic_vector(arg) std_logic_vector(arg) integer -> unsigned to_unsigned(arg,size) conv_unsigned(arg,size) integer -> signed to_signed(arg,size) conv_signed(arg,size) unsigned -> integer to_integer(arg) conv_integer(arg) signed -> integer to_integer(arg) conv_integer(arg) integer -> std_logic_vector integer -> unsigned/signed -> std_logic_vector std_logic_vector -> integer std_logic_vector -> unsigned/signed ->integer unsigned + unsigned -> std_logic_vector std_logic_vector(arg1 + arg2) arg1 + arg2 signed + signed -> std_logic_vector std_logic_vector(arg1 + arg2) arg1 + arg2 -- Literale fuer signed/unsigned to_unsigned(93, 8) "0011001100110011" -- bei signed mit Vorzeichen b"0011001100110011" -- Binaer x"F8C43E0" -- Hexadecimal -- synchron sequentielle Logik ABCffs: process (Clk, nResAsync) is -- erzeugt pro gespeicherten begin -- Signal ein flankenge- if nResAsync = cnActivated then -- steuertes D-FF A <= '0'; B <= '0'; C <= '0'; elsif Clk'event and Clk='1' then A <= NextA; B <= NextB; C <= NextC; end if; end process ABCffs; CalcNext: process (A, B, C) is -- rein kombinatorisch, begin -- also kein Speicher und NextA <= A and B; -- keine Latches! NextB <= B and C; NextC <= C and A; end process CalcNext; constant DefaultState : std_ulogic_vector(2 downto 0) := "000"; StateReg: process (Clk, nResAsync) is begin if nResAsync = cnActivated then State <= DefaultState; elsif Clk'event and Clk='1' then State <= NextState; end if; end process StateReg NextStateLogic: process (State) is begin case State is when "000" => NextState <= "100"; when "100" => NextState <= "010"; when "010" => NextState <= "001"; when "001" => NextState <= "011"; when "011" => NextState <= "111"; when "111" => NextState <= "000"; when others => NextState <= "XXX"; end process CalcNextState; -- synchron sequentielle Logik (1 Prozess) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.global.all; entity Counter is port (iResetAsync : in std_ulogic; iClk : in std_ulogic; oCount : out Unsigned(3 downto 0)); end entity Counter; architecture Rtl of Counter is signal Count : unsigned(3 downto 0); begin CountUp: process (iResetAsync, iClk) is begin if iResetAsync = cActivated then Count <= (others => '0'); elsif iClk'event and iClk='1' then if Count=x"9" then Count <= (others => '0'); else Count <= Count + 1; end if; end if; end process CountUp; oCount <= Count; end architecture Rtl; -- synchron sequentielle Logik (mit Eingaengen) architecture Rtl of Counter is signal Count : unsigned(3 downto 0); begin oCount <= Count; Counting: process (iResetAsync, iClk) is begin if iResetAsync = c then Count <= to_unsigned(0, Count’length); elsif iClk'event and iClk='1' then if iZero = cActivated then Count <= to_unsigned(0, Count’length); elsif iCountUp = cActivated then if Count = x"9" then Count <= to_unsigned(0, Count’length); else Count <= Count + 1; end if; else if Count = x"0" then Count <= x"9"; else Count <= Count - 1; end if; end if; end if; end process Counting; end architecture Rtl; -- Moore FSM package Global is constant cActivated : std_ulogic := ‘1’; constant cInctivated : std_ulogic := ‘0’; type aState is (Standing, WalkingForward, WalkingBackwards, Thinking); end package Global; library IEEE; use IEEE.std_logic_1164.all; use work.global.all; entity WalkAndThinkMachine is port(iResetAsync : in std_ulogic; iClk : in std_ulogic; iForth, iBack : in std_ulogic; oBusy : out std_ulogic; oState : out aState); end entity WalkAndThinkMachine; architecture Rtl of WalkAndThinkMachine is signal State, NextState : aState; begin oState <= State; NextStateAndOutput: process (State, iForth, iBack) is begin -- default settings NextState <= State; oBusy <= cInactivated; case State is when Standing => if iForth = cActivated then NextState <= WalkingForward; elsif iBack = cActivated then NextState <= WalkingBackwards; end if; when WalkingForward => if iForth = cActivated then NextState <= WalkingForward; elsif iBack = cActivated then NextState <= WalkingBackwards; end if; when WalkingBackwards => if iForth = cActivated then NextState <= Thinking; elsif iBack = cActivated then NextState <= WalkingBackwards; end if; when Thinking => oBusy <= cActivated; if iForth = cActivated then NextState <= Standing; end if; end case; end process NextStateAndOutput; StateReg: process (iResetAsync, iClk) is begin if iResetAsync = cActivated then State <= Standing; elsif iClk'event and iClk='1' then State <= NextState; end if; end process StateReg; end architecture Rtl; -- Mealy FSM package Global is constant cActivated : std_ulogic := ‘1’; constant cInctivated : std_ulogic := ‘0’; type aState is (WalkingForward, WalkingBackwards, Drinking); end package Global; library IEEE; use IEEE.std_logic_1164.all; use work.global.all; entity WalkAndDrinkMachine is port(iResetAsync : in std_ulogic; iClk : in std_ulogic; iForth, iBack : in std_ulogic; oGulp : out std_ulogic; oState : out aState); end entity WalkAndDrinkMachine; architecture Rtl of WalkAndDrinkMachine is signal State, NextState : aState; begin oState <= State; NextStateAndOutput: process (State, iForth, iBack) is begin -- default settings NextState <= State; oGulp <= cInactivated; case State is when Drinking => oGulp <= cActivated; if iForth = cActivated then NextState <= WalkingForward; elsif iBack = cActivated then NextState <= WalkingBackwards; end if; when WalkingForward => if iForth = cActivated then NextState <= WalkingForward; elsif iBack = cActivated then NextState <= Drinking; oGulp <= cActivated; end if; when WalkingBackwards => if iForth = cActivated then NextState <= Drinking; oGulp <= cActivated; end if; end case; end process NextStateAndOutput; StateReg: process (iResetAsync, iClk) is begin if iResetAsync = cActivated then State <= Drinking; elsif iClk'event and iClk='1' then State <= NextState; end if; end process StateReg; end architecture Rtl;